module control_unit (
    input           zero,
    input   [6:0]   op,
    input   [2:0]   funct3,
    input           funct7_5,

    output          pcsrc,
    output          reg_write,
    output  [2:0]   imm_src,
    output  [1:0]   alu_srcA,
    output  [1:0]   alu_srcB,
    output          mem_write,
    output  [3:0]   mem_write_mask,
    output          mem_en,
    output  [1:0]   result_src,
    output  [2:0]   alu_control
);

wire         branch;
wire         jump;
wire  [1:0]  alu_op;

assign pcsrc = (branch & zero) | jump;  //分支跳转

main_decoder u_main_decoder(
    .op             (op        ),
    .funct3         (funct3    ),
    .reg_write      (reg_write ),
    .imm_src        (imm_src   ),
    .alu_srcA       (alu_srcA  ),
    .alu_srcB       (alu_srcB  ),
    .mem_write      (mem_write ),
    .mem_write_mask (mem_write_mask),
    .mem_en         (mem_en    ),
    .result_src     (result_src),
    .branch         (branch    ),
    .alu_op         (alu_op    ),
    .jump           (jump      )
);  

alu_decoder u_alu_decoder(
    .op5            (op[5]      ),
    .funct3         (funct3     ),
    .funct7_5       (funct7_5   ),
    .alu_op         (alu_op     ),
    .alu_control    (alu_control)
);

endmodule
